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Open Drain Mode (OPD)
In a multimaster or multislave SPI system, the data output pins (
) can be configured to behave as open drain drivers to prevent conten-
MISO
tion and possible damage to pin drivers. An external pull-up resistor is
required on both the
When the
bit (13) is set and the SPI ports are configured as masters,
OPD
the
pin is three-stated when the data driven out on
MOSI
The
pin is not three-stated when the driven data is logic-low. A zero
MOSI
is driven on the
SPI ports are configured as slaves, the
driven out on
MISO
Normally, it is acceptable to enable (SRU) output buffers to permanently
assert the
PBEN_I
mode, because the DAI buffer always actively drives the output pin.
Where open drain mode is used for the
first connect the
SRU buffers. Programs must then tie the pin input signal to ground.
more information, see Chapter 5, Digital Application Interface.
Enable (SPIEN)
For SPI slaves, the slave-select input acts like a reset for the internal SPI
logic. For this reason, the
can also be used as a software reset of the internal SPI logic. An exception
to this is the W1C-type (write 1-to-clear) bits in the
These bits remain set if they are already set.
Always clear the W1C-type bits before re-enabling the SPI, as these
bits do not get cleared even if SPI is disabled. This can be done by
writing 0xFF to the
error, enable the SPI ports after
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
and
MOSI
MISO
pin in this case. Similarly, when
MOSI
is logic-high.
signals. However, this does not work for the open drain
signals to the pin enable associated with the SPIB
PBEN_I
line must be error free. The
SPIDS
SPISTATx
Serial Peripheral Interface Ports
pins when this option is selected.
OPD
pin is three-stated if the data
MISO
/
pins, programs must
MOSI
MISO
SPISTATx
registers. In the case of an MME
is deasserted.
SPIDS
and
MOSI
is logic-high.
MOSI
is set and the
For
signal
SPIEN
registers.
7-17
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