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Parallel Port Registers
FIFOs and high speed A/D and D/A converters and offers the maximum
throughput available on the parallel port (111M byte/sec).
In 16-bit mode, 16 bits (maximum) of external address are available
through latching the 16 bits of
during the
ALE
16 bits of data during the second half of the cycle when the
is asserted.
The
ALE
the address is driven and one peripheral clock cycle before the
address is received. This provides enough setup and hold time for
the 16-bit address with respect to
Figure 4-3
shows the connection diagram in 16-bit mode.
ADSP-2136x
Figure 4-3. External Transfer–16-bit Mode
Parallel Port Registers
The ADSP-2136x processor's parallel port contains several user-accessible
registers. The parallel port control register,
status bits and is described below.
4-10
www.BDTIC.com/ADI
A15–0
phase of the cycle. The
signal is deasserted one peripheral clock cycle (
AD[15-0]
16
LATCH
ALE
ALE
RD
WR
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
from
into the external latch
AD15–0
bits represent the external
AD15–0
.
ALE
SRAM
64K X 16
D[15-0]
16
Q
A[15-0]
RD
WR
, contains control and
PPCTL
or
signal
RD
WR
) after
PCLK
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