Table of Contents
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IDP
DMA index (IDP_DMA_Ix) register,
8-20,
8-21
DMA modify (IDP_DMA_Mx) register,
8-20,
8-21
FIFO (IDP_FIFO) register, 8-17, 8-18,
8-23,
A-53
FIFO memory data transfer,
FIFO register (IDP_FIFO register),
8-17,
A-53
illustrated,
8-2
interrupt driven transfers,
interrupts, 8-18,
8-27
memory data transfer,
multiplexed channels,
multiplexing, 8-4,
8-9
multiplexing register,
overflow, FIFO,
8-9
packing modes, 8-13,
PDAP control (IDP_PDAP_CTL)
register,
A-50
PDAP control (IDP_PP_CTL) register,
A-50
ping-pong DMA,
8-20
pin status register,
A-106
polarity of left-right encoding,
programming examples,
right-justified mode,
8-26
serial inputs,
8-4
throughput,
8-6
IDP bits
buffer hang disable (IDP_BHD),
bus hang disable (IDP_BHD),
clear buffer overflow (IDP_CLROVR),
A-48
data format (IDP_SMODEx),
DMA enable (IDP_DMA_EN), 8-27,
A-48
DMA status (IDP_DMAx_STAT),
8-22, 8-23, A-55,
A-80
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
(continued)
8-18
8-18
8-18
8-4
14-18
8-14
8-8
8-31
8-25
A-48
A-49
IDP bits
enable (IDP_ENABLE), 8-27, 8-28,
A-48
FIFO number of samples
(IDP_FIFOSZ), A-55,
FIFO samples exceed interrupt
(IDP_FIFO_GTN_INT),
frame sync format (IDP_SMODEx),
8-6, 8-26,
A-53
IDP_DMA_EN bit
do not set,
8-19
monitor number of samples
(IDP_NSET),
A-48
PDAP clock edge
(IDP_PDAP_CLKEDGE), 8-26,
A-52
PDAP enable (IDP_PDAP_EN), 8-28,
A-52
PDAP input mask bits,
PDAP packing mode
(IDP_PDAP_PACKING),
PDAP reset (IDP_PDAP_RESET),
A-52
ping-pong DMA enable (IDP_PING)
bits,
A-50
port select (IDP_PORT_SELECT),
A-51
port select (IDP_PP_SELECT),
reset (IDP_PDAP_RESET) bit,
IDP_CTL0 (input data port control)
register, 8-27,
A-47
IDP_CTL1 (input data port control)
register, 8-27, A-49,
IFS (internal frame sync select) bit, A-33,
A-41
IISPx (serial port DMA internal index)
registers, 2-6,
2-18
IMPP (parallel port DMA modify) register,
14-38
Index
(continued)
A-80
8-27
8-26
A-52
8-26
A-52
A-50
I-9
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