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16-Bit SPI Packing
Figure
14-13shows how a 16-bit SPI host packs 48-bit instructions at PM
addresses 0x90000 and 0x90001. For 16-bit hosts, two 16-bit words are
packed into the shift register to generate a 32-bit word. The 32-bit word
shifts to internal program memory during the kernel load.
The following code shows a 48-bit instruction executed.
[0x90000] 0x112233445566
[0x90001] 0x7788AABBCCDD
MOSI/MISO
Figure 14-13. 16-Bit SPI Master/Slave Packing
The 16-bit SPI host packs or prearranges the data as:
SPI word 1 =
0x5566
SPI word 2 =
0x3344
SPI word 3 =
0x1122
SPI word 4 =
0xCCDD
SPI word 5 =
0xAABB
SPI word 6 =
0x7788
The initial boot of the 256-word loader kernel requires a 16-bit host to
transmit 768 16-bit words. Two packed 16-bit words comprise the 32-bit
word. The SPI DMA count value of 0x180 is equivalent to 384 words.
Therefore, the total number of 16-bit words loaded is 768.
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
32
32
DMA
System Design
Internal
32
Memory
(Loader Kernel)
(IVT)
14-45
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