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AES/EBU/SPDIF Formats
Channel Coding
To minimize the direct-current (dc) component on the transmission line,
to facilitate clock recovery from the data stream, and to make the interface
insensitive to the polarity of connections, time slots 4 to 31 are encoded in
bi-phase mark.
Each bit to be transmitted is represented by a symbol comprising two con-
secutive binary states. The first state of a symbol is always different from
the second state of the previous symbol. The second state of the symbol is
identical to the first if the bit to be transmitted is logic 0. However, it is
different if the bit is logic 1.
Figure C-6
shows that the ones in the original data end up with mid cell
transitions in the bi-phase mark encoded data, while zeros in the original
data do not. Note that the bi-phase mark encoded data always has a transi-
tion between bit boundaries.
CLOCK
(2 TIMES BIT RATE
DATA
BI-PHASE-MARK
DATA
Figure C-6. Bi-phase Mark Encoding
C-14
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ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
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