Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 577

Table A-44. Group C Sources – Frame Sync (Cont'd)
Selection Code Source Signal
11010 (0x1A) DIR_FS_O
11011 (0x1B) DIT_O
11100 (0x1C) PCG_FSA_O
11101 (0x1D) PCG_FSB_O
11110 (0x1E) LOW
11111 (0x1F) HIGH
Pin Signal Assignment Registers
(SRU_PINx, Group D)
Each physical pin (connected to a bonded pad) may be routed using the
pin signal assignment registers (see
the SRU to any of the inputs or outputs of the DAI peripherals, based on
the 7-bit values listed in
signals that control the pins in other ways.
31 30 29 28 27 26 25 24
DAI_PB04_I (27–21)
DAI Pin Buffer 4 Input
15 14 13 12
DAI_PB03_I (20–14)
DAI_PB02_I (13–7)
DAI Pin Buffer 2 Input
Figure A-55. SRU_PIN0 Register
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Description (Source Selection)
SPDIF RX frame sync output
SPDIF TX biphase encoded output
Precision frame sync A output
Precision frame sync B output
Logic level low (0)
Logic level high (1)
Figure A-55
Table A-45. The SRU also may be used to route
23 22 21 20 19 18 17 16
11 10 9 8 7 6 5 4
Registers Reference
through Figure
DAI_PB03_I (20–14) (con't)
DAI Pin Buffer 3 Input
3 2 1 0
DAI_PB01_I (6–0)
DAI Pin Buffer 1 Input
A-59) in
A-93