Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 327

Table of Contents

Figure 9-8. EXT_CLK Timing

This section describes all relevant registers and hardware to raise and ser-

vice interrupts.

Each timer generates a unique interrupt request signal. A common register

latches these interrupts so that a program can determine the interrupt

source without reference to the timer's interrupt signal. The

ter contains an interrupt latch bit (

indicator bit (

These sticky bits are set by the timer hardware and may be watched by

software. They need to be cleared in the

itly. To clear, write a one to the corresponding bit in the

in the following example.

ADSP-2136x SHARC Processor Hardware Reference

www.BDTIC.com/ADI

for the ADSP-21362/3/4/5/6 Processors

) for each timer.

Peripheral Timers

) and an overflow/error