Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 532

Peripherals Routed Through the DAI
Table A-19. IDP_CTL0 Register Bit Descriptions
Bits Name
3–0 IDP_NSET
4 IDP_BHD
5 IDP_DMA_EN
6 IDP_CLROVR
7 IDP_EN
A-48
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Description
Threshold Interrupt. The contents of the IDP_NSET bits represent
a threshold number of entries (N) in the FIFO. When the FIFO fills
to a point where it has more (N+1) than N words (data in FIFO
exceeds the value set in the IDP_NSET bit field), a DAI interrupt is
generated. This DAI interrupt corresponds to the
IDP_FIFO_GTN_INT bit in DAI_IRPTL_x registers.
Only the core can use this N threshold interrupt to detect when data
needs to be read. The maximum IDP_NSET= 7, otherwise no inter-
rupt is generated.
IDP Buffer Hang Disable. Reads of an empty FIFO or writes to a
full FIFO to cause a core hang. This condition continues until the
FIFO has valid data (in the case of reads) or the FIFO has at least
one empty location (in the case of writes). Note this can be used in
debug operations.
0 = Core hang is enabled
1 = Core hang is disabled
DMA Enable. Enables DMA on all IDP channels. This bit is the
global control for standard and ping-pong DMA.
0 = Channel disabled
1 = Channel enabled
FIFO Overflow Clear Bit. Writes of 1 to this bit clear the overflow
condition in the DAI_STAT0 register. Because this is a WO-bit, it
always returns 0 when read.
Enable IDP. This bit enables the IDP. This is a global control bit.
This bit needs to be set for all operations modes including DMA.
When this bit is cleared (= 0), the IDP is disabled, and data cannot
move to the IDP_FIFO.
Note that when the IDP_EN bit transitions from 1 to
0, all data in the IDP FIFO are flushed. Writing a 1 to bit 31 of the
IDP_CTL1 register also flushes the FIFO. This is a WO-bit and
always returns a zero on reads.
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors