I/O Processor Register Access; Iop Access Conditions - Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual

I/O Processor Register Access

I/O Processor Register Access
All of the I/O processor's registers are memory-mapped, ranging from
address 0x0000 0000 to 0x0003 FFFF.

IOP Access Conditions

The IOP registers are physically located in two clock domains.
1. Core domain (
more information, see "Registers Reference" in Chapter A, Regis-
ters Reference.
2. Peripheral domain (
the peripheral domain (core/2 clock). This means that there are
different access conditions which are explained in this section.

Accesses to IOP registers (from the processor core) should not use
Type 1 (dual access) or LW instructions.

I/O processor registers have an effect latency range from one to six
cycles (changes take minimum effect on the second cycle or maxi-
mum effect after seven cycles).
Table 2-16. I/O Processor Access Conditions
Type Of Access
IOP register write/read
IOP register back to back write/read
Conditional IOP register write/read
Aborted IOP register write/read
2-32
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)— and all user breakpoint registers.
CCLK SYSCTL
)—All other IOP registers are located in
PCLK
Core Domain (Core
Cycles)
1/2
1/2
1/2
2/3
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
For
Peripheral Domain
(Core Cycles)
1/8
2/8
3/10
4/4