Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 319

Table of Contents

On invalid conditions, the timer sets both the

bits and the Count register is not altered. Note that after reset, the timer

registers are all zero. The PWM_OUT timing is shown in

As mentioned earlier, 2 x

is the width. If the period and width values are valid after the

timer is enabled, the count register is loaded with the value resulting from

0xFFFF FFFF – width. The timer counts upward to 0xFFFF FFFF.

Instead of incrementing to 0xFFFF FFFF, the timer then reloads the

counter with the value derived from 0xFFFF FFFF – (period – width) and

Figure 9-3. PWM_OUT Timing

ADSP-2136x SHARC Processor Hardware Reference

www.BDTIC.com/ADI

for the ADSP-21362/3/4/5/6 Processors

is the period of the PWM waveform and

Peripheral Timers