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Functional Description
For normal operation, the data, clock, and frame sync signals need to be
routed as shown in
Table 12-3. SRC DAI/SRU Signal Routing
Internal Node
Inputs
SRC3–0_CLK_IP_I
SRC3–0_CLK_OP_I
SRC3–0_FS_IP_I
SRC3–0_FS_OP_I
SRC3–0_DAT_IP_I
SRC3–0_TDM_OP_I
Outputs
SRC3–0_DAT_OP_O
SRC3–0_TDM_IP_O
For information on using the SRU, see
page
5-16.
Functional Description
Figure 12-1
shows a top level block diagram of the SRC module and
Figure 12-2
shows architecture details. The sample rate converter's FIFO
block adjusts the left and right input samples and stores them for the FIR
filter's convolution cycle. The SRCx_FS_IP counter provides the write
address to the FIFO block and the ramp input to the digital-servo loop.
The ROM stores the coefficients for the FIR filter convolution and per-
forms a high-order interpolation between the stored coefficients. The
sample rate ratio block measures the sample rate by dynamically altering
the ROM coefficients and scaling the FIR filter length and input data.
The digital-servo loop automatically tracks the
12-4
www.BDTIC.com/ADI
Table
12-3.
DAI Connection
Group A
Group C
Group B
Group B, D
Group B
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
SRU Register
SRU_CLK2–1
SRU_FS2–1
SRU_DAT3–2
"Rules for SRU Connections" on
SRCx_FS_IP
and
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