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The resulting on-times (active low) of the PWM signals over the full
PWM period (two half periods) produced by the PWM timing unit and
illustrated in
Figure 10-5 on page 10-16
The range of T
and the corresponding duty cycles are:
T
PWMPERIOD
(
=
AH
The range of T
T
(
PWMPERIOD 2
=
AL
and the corresponding duty cycles are:
d AH
d AL
The minimum permissible value of T
sponds to a 0% duty cycle, and the maximum value is T
switching period, which corresponds to a 100% duty cycle. Negative val-
ues are not permitted.
The output signals from the timing unit for operation in double-update
mode are shown in
switching frequency, dead time, and duty cycle are all changed in the sec-
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
is:
AH
[
×
–
0 2
PWMPERIOD
+
2
PWMCHA P
×
(
is:
AL
(
–
×
T AH
1
PWMCHA P
----------- -
-- -
----------------------------------------------------- -
=
+
=
T S
2
T AL
1
PWMCHA
---------- -
-- -
-------------------------------------------------------- -
=
–
=
T S
2
Figure
10-5. This illustrates a general case where the
Pulse Width Modulation
may be written as:
×
t PCLK ]
– WMDT
+
PWMCHA
PWMDT
– WMDT
PWMPERIOD
+
PWMDT
PWMPERIOD
and T
is zero, which corre-
AH
AL
)
t PCLK
)
×
) )
×
t
PCLK
, the PWM
S
10-15
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