Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 320

Table of Contents

PWM Waveform Generation

bit is set, the internally-clocked timer generates rectangular

signals with well-defined period and duty cycles. This mode also generates

periodic interrupts for real-time processing.

The 32-bit period (

with the values of the timer count period and pulse width modulated out-

put pulse width.

When the timer is enabled in this mode, the

deasserted state each time the pulse width expires, and the signal is

asserted again when the period expires (or when the timer is started).

To control the assertion sense of the

corresponding

level) or set (causes a high assertion level).

When enabled, a timer interrupt is generated at the end of each period. An

ISR must clear the interrupt latch bit

and/or width values. In pulse width modulation applications, the program

needs to update the period and pulse width values while the timer is

When a program updates the timer configuration, the

must always be written to last, even if it is necessary to update only

one of the registers. When the

the ISR reads the current value of the

again. On the next counter reload, all of the timer control registers

are read by the timer.

To generate the maximum frequency on the

the period value to two and the pulse width to on e. This makes the

signal toggle every 2

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) and width (

clock cycles as shown in

ADSP-2136x SHARC Processor Hardware Reference

for the ADSP-21362/3/4/5/6 Processors

) registers are programmed

signal is pulled to a

and might alter period

value is not subject to change,

output signal, set

9-9. Assuming