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Peripherals Routed Through the DAI
Each timer is provided with its own sticky status register
enable or disable an individual timer, the
example, writing a one to bit 8 sets the
clears it. Writing a one to both bit 8 and bit 9 clears
status register returns the
remaining
TIMxEN
15 14 13 12
TIM2DIS (W1C)
Timer 2 Disable
TIM2EN
Timer 2 Enable
TIM1DIS (W1C)
Timer 1 Disable
TIM1EN
Timer 1 Enable
TIM0DIS (W1C)
Timer 0 Disable
TIM0EN
Timer 0 Enable
TIM2OVF
Timer 1 Counter Overflow Error
Figure A-26. TMxSTAT Register
Table A-26. TMxSTAT Register Bit Descriptions
Bit
Name
0
TIM0IRQ Timer 0 Interrupt Latch
1
TIM1IRQ Timer 1 Interrupt Latch
2
TIM2IRQ Timer 2 Interrupt Latch
3
Reserved
4
TIM0OVF Timer 0 Overflow/Error
5
TIM1OVF Timer 1 Overflow/Error
6
TIM2OVF Timer 2 Overflow/Error
7
Reserved
8
TIM0EN Timer 0 Enable
A-58
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state on both bit 8 and bit 9. The
TIM0EN
bits operate similarly.
11 10
9
8
7
6
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
TIMxEN
bit is set or cleared. For
TIMxEN
bit; writing a one to bit 9
TIM0EN
TIM0EN
5
4
3
2
1
0
TIM0IRQ (W1C)
Timer 0 Interrupt
TIM1IRQ (W1C)
Timer 1 Interrupt
TIM2IRQ (W1C)
Timer 2 Interrupt
TIM0OVF
Timer 0 Counter
Overflow Error
TIM1OVF
Timer 1 Counter
Overflow Error
Description
Write one-to-clear (also an output)
Write one-to-clear (also an output)
Write one-to-clear (also an output)
Write one-to-clear (also an output)
Write one-to-clear (also an output)
Write one-to-clear (also an output)
Write one to enable timer 0
bit. To
. Reading the
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