Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 521

Table A-16. SPCTLx Register Bit Descriptions (I
Left-Justified) (Cont'd)
Bit Name
9 PACK
10 MSTR
11 OPMODE
14–12 Reserved
15 DIFS
16 L_FIRST
17 LAFS
18 SDEN_A
19 SCHEN_A
20 SDEN_B
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Description
16-bit to 32-bit Word Packing Enable.
0 = Disable 16- to 32-bit word packing
1 = Enable 16- to 32-bit word packing
Master Clock Select.
0 = Select external clock and frame sync
1 = Select internal clock and frame sync
Sport Operation Mode.
2
1 = Selects the I S or left-justified mode
Bit 17 is used to select either of both modes
Data Independent Frame Sync Select.
0 = Serial port uses a data-dependent frame sync (sync when TX FIFO
is not empty or when RX FIFO is not full).
1 = Serial port uses a data-independent frame sync (sync at selected
interval)
Left Channel Word First Select. Selects left or right channel Word
first. To select the channel order, set the L_FIRST bit (= 1) to transmit
or receive on left channel first, or clear the L_FIRST bit (= 0) to trans-
mit or receive on right channel first.
I2S or Left-Justified Mode Select.
0 = I2S mode
1 = Left-justified mode
See also bit 11 of this register.
Enable Channel A Serial Port DMA.
0 = Disable serial port channel A DMA
1 = Enable serial port channel A DMA
Enable Channel A Serial Port DMA Chaining.
0 = Disable serial port channel A DMA chaining
1 = Enable serial port channel A DMA chaining
Enable Channel B Serial Port DMA.
0 = Disable serial port channel B DMA
1 = Enable serial port channel B DMA
Registers Reference
2
S,
A-37