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Peripheral Registers
DMA Configuration Registers (SPIDMAC, SPIDMACB)
These 17-bit SPI registers are used to control DMA transfers and are
shown in
Figure A-6
31 30 29 28 27 26 25 24
SPICHS
DMA Chain Loading Status
15 14 13 12
SPIDMAS
DMA Transfer Status
SPIERRS
DMA Error Status
SPISx (13–12)
DMA FIFO Status
SPIMME
Multimaster Error
SPIUNF
Transmit Underflow Error SPIRCV=1)
SPIOVF
Receive Overflow Error (SPIRCV=1)
Figure A-6. SPIDMAC, SPIDMACB Registers
Table A-5. SPIDMAC, SPIDMACB Register Bit Descriptions
Bit
Name
0
SPIDEN
1
SPIRCV
2
INTEN
3
Reserved
A-18
www.BDTIC.com/ADI
and described in
Table
23 22 21 20 19 18 17 16
11 10
9
8
7
6
Description
DMA Enable.
0 = Disable
1 = Enable
DMA Write/Read.
0 = SPI transmit (read from internal memory)
1 = SPI receive (write to internal memory)
Enable DMA Interrupt on Transfer.
0 = Disable
1 = Enable
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
A-5.
5
4
3
2
1
0
SPIDEN
DMA Enable
SPIRCV
DMA Write/Read
INTEN
Enable DMA Interrupt on Transfer
SPICHEN
SPI DMA Chaining Enable
FIFOFLSH
DMA FIFO Clear
INTERR
Enable Interrupt on Error
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