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Internal Memory Kernel Load
The internal memory blocks of SHARC processors are based on 4 col-
umns, each of which is 16-bits in I/O wi d th. The access type is defined on
the address space (for example short word address space only performs a
one column access). Different addressing modes result in different address
counts (for example one long word address represents four short word
addresses). The four different access types are:
• 1-column access (short word, 16-bit)
• 2-column access (normal word, 32-bit)
• 3-column access (normal word, 48-bit)
• 4-column access (long word, 64-bit)
During the boot process, word packing of 8 to 32-bit is performed. In
other words, the kernel is not loaded directly with 256 x 48-bit words,
instead it is loaded with 384 x 32-bit 'packed words' (2-column access).
Note that the sequencer considers the IVT as opcode and fetches the block
in 3-column mode, (or 48-bit instructions).
The same physical IVT space is booted by DMA in 2 column
(
IVT_START_ADDR
sequencer in 3-column (
more information about 32- and 48-bit internal memory address-
ing, see the "Memory" chapter in the SHARC Processor
Programming Reference.
For the ADSP-2136x SHARC processors
= 0x900FF.
IVT_END_ADDR
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
– (
IVT_START_ADDR
IVT_START_ADDR
IVT_START_ADDR
System Design
+ 0x17F)) and fetched by the
–
IVT_END_ADDR
= 0x90000 and
). For
14-35
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