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a maximum programmed dead time of:
=
Td, max
1023 2
This equates to an
grammed to zero by writing 0 to the
Time Registers (PWMDTx)" on page
Duty Cycles
The two 16-bit read/write duty cycle registers,
duty cycles of the four PWM output signals on the PWM pins when not
in switch reluctance mode. The two's-complement integer value in the
register controls the duty cycle of the signals on the
PWMA
. The two's-complement integer value in the
PWM_AL
the duty cycle of the signals on
registers are programmed in two's-complement integer counts of the fun-
damental time unit,
PWM signal produced by the two-phase timing unit over half the PWM
period. The duty cycle register range is from:
(–PWPERIOD ÷ 2 – PWMDT) to (+PWPERIOD ÷ 2 + PWMDT)
which, by definition, is scaled such that a value of 0 represents a 50%
PWM duty, cycle. The switching signals produced by the two-phase tim-
ing unit are also adjusted to incorporate the programmed dead time value
in the
register. The two-phase timing unit produces active low
PWMDT
signals so that a low level corresponds to a command to turn on the associ-
ated power device.
Duty Cycles and Dead Time
A typical pair of PWM outputs (in this case for
the timing unit are shown in
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
×
×
=
t
1023
PCLK
rate of 100 MHz. Note that dead time can be pro-
PCLK
PWM_BH
, and define the desired on-time of the high-side
PCLK
Figure 10-4
Pulse Width Modulation
9 –
×
×
×
2
10
10
registers (see
PWMDTx
A-29).
and
PWMA
PWMB
and
pins. The duty cycle
PWM_BL
and
PWM_AH
for operation in single-update
=
20.5micro sec
"PWM Dead
, control the
PWMB
and
PWM_AH
register controls
) from
PWM_AL
10-13
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