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Table A-33. DITCTL Register Bit Descriptions
Bit
Name
0
DIT_EN
1
DIT_MUTE
3–2
DIT_FREQ
4
DIT_SCDF
5
DIT_SCDF_LR
8–6
DIT_SMODEIN
9
DIT_AUTO
10
DIT_VALIDL
11
DIT_VALIDR
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Description
Transmitter Enable. Enables the transmitter and resets the
control registers to their defaults.
0 = Transmitter disabled
1 = Transmitter enabled
Mute. Mutes the serial data output.
Frequency Multiplier. Sets the over sampling ratio to the fol-
lowing:
00 = 256 x frame sync
01 = 384 x frame sync
10, 11 = Reserved
Single-channel, Double-frequency Mode Enable.
0 = 2 channel mode
1 = SCDF mode
Select Single-channel, Double-frequency Mode.
0 = Left channel
1 = Right channel
Serial Data Input Format. Selects the input format as follows:
000 = Left-justified
2
001 = I
S
010 = reserved
011 = reserved
100 = Right-justified, 24-bits
101 = Right-justified, 20-bits
110 = Right-justified, 18-bits
111 = Right-justified, 16-bits
Automatically Generate Block Start. Automatically generate
block start. When enabled, the transmitter is in standalone
mode where it inserts block start, channel status, and validity
bits on its own.
0 = Manually start block transfer according to input stream
status bits
1 = Automatically start block transfer.
Validity Bit A. Use with channel status buffer.
Validity Bit B. Use with channel status buffer.
Registers Reference
A-71
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