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ustat3 = DMISO|
WL32|
SPIMS|
SPIEN|
TIMOD2;
dm(SPICTL) = ustat3;
ustat3 = SPIDEN; dm(SPIDMAC) = ustat3;
_main.end: jump (pc,0);
Listing 7-3. SPI DMA Chaining Example
.section/dm seg_dmda;
/* Destinations for incoming data */
.var dest_bufC[8];
.var dest_bufB[8];
.var dest_bufA[8];
/* Transfer Control Blocks (TCB's) */
.var first_tcb[] =
(0x7FFFF&second_tcb + 3),
LENGTH(dest_bufB),
1,
dest_bufB;
.var second_tcb[] = 0,
LENGTH(dest_bufC),
1,
dest_bufC;
/* NOTE: Chain Pointer registers must point to the LAST
location in the TCB, "tcb + 3". */
/*Main code section */
.global _main;
.section/pm seg_pmco;
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Serial Peripheral Interface Ports
/* Disable MISO on transfers */
/* 32-bit words */
/* Master mode (internal SPICLK) */
/* Enable SPI port */
/* Initialize SPI port to begin
transmitting when DMA is enabled */
/* for CPSPI (next tcb) */
/* for CSPI (next count) */
/* for IMSPI (next modify) */
/* for IISPI (next index) */
/* null CPSPI ends chain */
/* count for final DMA */
/* IM for final DMA */
/* II for final DMA */
/* begin DMA */
7-47
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