Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 540

Table of Contents

Peripherals Routed Through the DAI

IDP Status Register 1 (DAI_STAT1)

Since the core does allow writes to the

described in

maximum of 8 entries each.

Table A-24. DAI_STAT1 Register Bit Descriptions

Peripheral Timer Registers

The timer peripheral module provides general-purpose timer functional-

ity. It consists of three identical timer units. Each timer has

memory-mapped registers described in the following sections. Each timer

also has two 32-bit count registers decsribed in

Timer Configuration Registers (TMxCTL)

All timer clocks are gated off when the specific timer's configuration regis-

ter is set to zero at system reset or subsequently reset by user programs.

These registers are shown in

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A-24, stores the different read or writes indexes with a

Write Index Pointer. Reflects the write index status during

core writes to the IDP_FIFO.

0000 = no write done

1000 = 8 writes done

Read Index Pointer. Reflects the read index status during

core reads from the IDP_FIFO.

0000 = no read done

1000 = 8 reads done

ADSP-2136x SHARC Processor Hardware Reference

for the ADSP-21362/3/4/5/6 Processors

"Count Registers" on