Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 433

/* Enable DAI Pins 1 & 2 as outputs */
r0 = (PBEN_HIGH_Of|(PBEN_HIGH_Of<<DAI_PBOE2));
dm(SRU_PBEN0) = r0;
r0 = ENCLKA; /* Enable PCG Channel A Clock, No Channel A FS */
/* FS Divisor = 0, FS Phase 10–19 = 0 */
dm(PCG_CTLA1) = r0;
r1 = 0xfffff; /* Clk Divisor = 0xfffff, FS Phase 0-9 = 0 */
/* Use CLKIN as clock source */
dm(PCG_CTLA0) = r1;
r0 = (5<<PCG_PWB); /* PCG Channel B FS Pulse width = 1 */
dm(PCG_PW) = r0;
r0 = (ENFSB|ENCLKB|10); /*Enable PCG Channel B Clock and FS*/
/* FS Divisor = 10, FS Phase 10-19 = 0 */
dm(PCG_CTLB1) = r0;
r0 = (CLKBSOURCE|FSBSOURCE|10); /* Clk Divisor = 10 */
/* FS Phase 0-9 = 0, Use SRU_MISC4 as clock source */
dm(PCG_CTLB0) = r0;
_main.end: jump(pc,0);
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Precision Clock Generator
13-25