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Table 2-14. Parallel Port TCBs (Cont'd)
Address
CP[18:0] – 0x4
CP[18:0] – 0x5
CP[18:0] – 0x6
For more information on programming DMA, refer to the specific periph-
eral chapters.
For the parallel port chain pointer, the TCB location is not at the
beginning of the TCB list.
SPI TCB
The serial peripheral interfaces supports both single and chained DMA.
However, unlike the serial ports, programs cannot insert a TCB in an
active chain.
Table 2-15
Table 2-15. SPI/SPIB TCBs
Address
CP[18:0]
CP[18:0] – 0x1
CP[18:0] – 0x2
CP[18:0] – 0x3
ADSP-2136x SHARC Processor Hardware Reference
www.BDTIC.com/ADI
for the ADSP-21362/3/4/5/6 Processors
Register
EIPP External Index
EMPP External Modifier
ECPP External Count
shows the required TCB for chained DMA.
Register
IISPI/B Internal Index
IMSPI/B Internal Modifier
ICSPI/B Internal Count
CPSPI/B Chain Pointer
I/O Processor
2-31
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