Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 426

Programming Examples

The combined PCGs can provide a selection of synchronous clock
frequencies to support alternate sample rates for the SRCs and
external DACs. However, the range of choices is limited by
and the ratio of
256:64:1 to support digital audio, left-justified, I
right-justified interface modes. Many DACs also support 384, 512,
and 786 ×
flexibility in choosing
Note also that in all three DAI modes, the falling edge of
must always be synchronous with both edges of
requires that the phase of the
be adjustable.
While the frequency of
sample rate supplied to the external DAC, there is no fixed-phase
requirement. For complete timing information, see the
ADSP-2136x SHARC Processor Data Sheet.
Figure 13-6 shows an example of the internal interconnections between
the S/PDIF receiver, SRC, and the PCGs. The interconnections are made
by programming the signal routing unit. Note that in this example,
set at 242 MHz. This frequency can be adjusted up to the maximum
for the chosen processor. Also note that master clock (
source provided for the PCG. This input can come from
peripheral output, or from one of the DAI pins.
13-18
www.BDTIC.com/ADI
PCG_CLKx_O:SCLK:FSYNC
for
FSYNC PCG_CLKx_O
.
CLKIN
SCLK
PCG_CLKx_O
ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
which is normally fixed at
2
S, and
, which allows some additional
FSYNC
and for a common PCG
FSYNC
must be synchronous with the
MCLK
CLKIN
CLKIN
SCLK
. This
is
CCLK
CCLK
) is the input
, any