Analog Devices SHARC ADSP-2136 Series Hardware Reference Manual page 205

Table of Contents

Receive Selection Registers

Setting a particular bit to 1 in the

causes the serial port to receive the word in that channel's position of the

data stream. The received word is loaded into the receive buffer. Clearing

the bit in the register causes the serial port to ignore the data.

Data Transfer Types

Serial port data can be transferred for use by the processor in two different

• Core-driven single word transfers

• DMA transfers between both internal and external memory

DMA transfers can be set up to transfer a configurable number of serial

words between the serial port buffers (

) and internal memory automatically. Core-driven transfers use

SPORT interrupts to signal the processor core to perform single word

transfers to/from the serial port buffers (

Core Transfers

The following sections provide information on core driven data transfers.

Single Word Transfers

Individual data words may also be transmitted and received by the serial

ports, with interrupts occurring as each 32-bit word is transmitted or

received. When a serial port is enabled and DMA is disabled, the SPORT

interrupts are generated whenever a complete 32-bit word has been

received in the receive buffer, or whenever the transmit buffer is not full.

ADSP-2136x SHARC Processor Hardware Reference

www.BDTIC.com/ADI

for the ADSP-21362/3/4/5/6 Processors

Serial Ports