Gpioh Output Speed Register (Gpioh_Ospeedr); Gpioh Pull-Up/Pull-Down Register (Gpioh_Pupdr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Table of Contents

Bits 31:4 Reserved, must be kept at reset value.

Bit 3 OT3: Port PH3 output type configuration

Bits 2:0 Reserved, must be kept at reset value.

GPIOH output speed register (GPIOH_OSPEEDR)

Address offset: 0x1C08

Reset value: 0x0000 0000

Bits 31:8 Reserved, must be kept at reset value.

Bits 7:6 OSPEED3[1:0]: Port PH3 output speed configuration

Note: Refer to the device datasheet for the frequency specifications and the power supply

Bits 5:0 Reserved, must be kept at reset value.

Address offset: 0x1C0C

Reset value: 0x0000 0000

These bits are written by software to configure the I/O output type.

0: Output push-pull (reset state)

1: Output open-drain

These bits are written by software to configure the I/O output speed.

00: Low speed

01: Medium speed

10: Fast speed

11: High speed

and load conditions for each speed.

OSPEED3[1:0]

RM0453 Rev 1

General-purpose I/Os (GPIO)

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