Gpioc Alternate Function High Register (Gpioc_Afrh); Gpioc Bit Reset Register (Gpioc_Brr) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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GPIOC alternate function high register (GPIOC_AFRH)

Address offset: 0x0824

Reset value: 0x0000 0000

AFSEL15[3:0]

Bits 31:28 AFSEL15[3:0]: Port PC15 alternate function selection

Bits 27:24 AFSEL14[3:0]: Port PC14 alternate function selection

Bits 23:20 AFSEL13[3:0]: Port PC13 alternate function selection

These bits are written by software to configure alternate function I/Os.

0x0: AF0 selected

0x1: AF1 selected

0x2: AF2 selected

0xE: AF14 selected

0xF: AF15 selected

Bits 19:0 Reserved, must be kept at reset value.

Address offset: 0x0828

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bit 15 BR15: Port PC15 reset output data bit [15] in GPIOC_ODR

Bit 14 BR14: Port PC14 reset output data bit [14] in GPIOC_ODR

Bit 13 BR13: Port PC13 reset output data bit [13] in GPIOC_ODR

Bits 12:7 Reserved, must be kept at reset value.

Bit 6 BR6: Port PC6 reset output data bit [6] in GPIOC_ODR

Bit 5 BR5: Port PC5 reset output data bit [5] in GPIOC_ODR

Bit 4 BR4: Port PC4 reset output data bit [4] in GPIOC_ODR

Bit 3 BR3: Port PC3 reset output data bit [3] in GPIOC_ODR

AFSEL14[3:0]

AFSEL13[3:0]

RM0453 Rev 1

General-purpose I/Os (GPIO)

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