Gpioc Alternate Function Low Register (Gpioc_Afrl) - ST STM32WL5 Series Reference Manual

General-purpose I/Os (GPIO)
Bit 2 LCK2: Port PC2 lock configuration
Bit 1 LCK1: Port PC1 lock configuration
Bit 0 LCK0: Port PC0 lock configuration
10.4.20

GPIOC alternate function low register (GPIOC_AFRL)

Address offset: 0x0820
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
AFSEL3[3:0]
rw rw rw
Bits 31:28 Reserved, must be kept at reset value.
Bits 27:24 AFSEL6[3:0]: Port PC6 alternate function selection
Bits 23:20 AFSEL5[3:0]: Port PC5 alternate function selection
Bits 19:16 AFSEL4[3:0]: Port PC4 alternate function selection
Bits 15:12 AFSEL3[3:0]: Port PC3 alternate function selection
Bits 11:8 AFSEL2[3:0]: Port PC2 alternate function selection
Bits 7:4 AFSEL1[3:0]: Port PC1 alternate function selection
Bits 3:0 AFSEL0[3:0]: Port PC0 alternate function selection
These bits are written by software to configure alternate function I/Os.
0x0: AF0 selected
0x1: AF1 selected
0x2: AF2 selected
...
0xE: AF14 selected
0xF: AF15 selected
416/1461
This bit is read/write but can only be written when the LCKK bit is 0.
0: Port PC0 configuration not locked
1: Port PC0 configuration locked
28 27 26 25
Res. AFSEL6[3:0]
rw rw rw
12 11 10 9
AFSEL2[3:0]
rw rw rw rw
24 23 22
AFSEL5[3:0]
rw rw rw
8 7 6
AFSEL1[3:0]
rw rw rw
RM0453 Rev 1
21 20 19 18
AFSEL4[3:0]
rw rw rw rw
5 4 3 2
AFSEL0[3:0]
rw rw rw rw
RM0453
17 16
rw rw
1 0
rw rw