Bit Timing Register (Btr); Fig. 23.3 Bit Time Segment In Can Specification; Fig. 23.4 Bit Time Segment In Can Controller - Fujitsu MB90420/5 (A) Series Hardware Manual

23.6.5 Bit Timing Register (BTR)

Bit timing register (BTR) sets the prescaler and bit timing setting.
n Bit timing register (BTR)
Address: 003C07 (CAN0)
H
Address: 003D07 (CAN1)
H
Read/write →
Initial value →
Address: 003C06 (CAN0)
H
Address: 003D06 (CAN1)
H
Read/write →
Initial value →
Note: This register should be set during bus operation stop (HALT = 1).
[bits 14 to 12] TS2.2 to TS2.0: Time segment 2 set bits 2 to 0
These bits divide the time quanta (TQ) by [(TS2.2 to TS2.0) +1] for determination of the time segment 2
(TSEG2). The time segment 2 is equal to the phase buffer segment 2 (PHASE_SEG2) in the CAN
specification.
[bits 11 to 8] TS1.3 to TS1.0: Time segment 1 set bits 3 to 0
These bits divide the time quanta (TQ) by [(TS1.3 to TS1.0) +1] for determination of the time segment
(TSEG1). The time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer
segment 1 (PHASE_SEG1) in the CAN specification.
[bits 7 and 6] RSJ1 and RSJ0: Resynchronization jump width set bits 1 and 0
These bits divide the time quanta (TQ) by [(RSJ1 to RSJ0) +1] for determination of the resynchronous
jump width.
[bits 5 to 0] PSC5 to PSC0: Prescaler set bits 5 to 0
These bits divide the input clock by frequency of [(PSC5 to PSC0) +1] for determination of the time
quanta of CAN controller.
The bit time segments defined in the CAN specification, and the CAN controller are shown in Figures
23.3 and 23.4 respectively.
CAN CONTROLLER
15 14
— TS2.2 TS2.1
(—) (R/W) (R/W)
(—) (1)
7 6
RSJ1 RSJ0 PSC5
(R/W) (R/W) (R/W)
(1) (1)
Nominal bit time
S YNC_ S E G PROP_SEG P HAS E _ S E G1 P HAS E _ S E G2

Fig. 23.3 Bit Time Segment in CAN Specification

Nominal bit time
S YNC_ S E G

Fig. 23.4 Bit Time Segment in CAN Controller

13 12 11
TS2.0 TS1.3
(R/W) (R/W)
(1) (1) (1)
5 4 3
PSC4 PSC3
(R/W) (R/W)
(1) (1) (1)
Sample point
T S E G1 T S E G2
Sample point
23-17
10 9 8
TS1.2 TS1.1 TS1.0
(R/W) (R/W) (R/W)
(1) (1) (1)
2 1 0
PSC2 PSC1 PSC0
(R/W) (R/W) (R/W)
(1) (1) (1)
← Bit No.
← Bit No.