Operation Of The 16-Bit Reload Register - Fujitsu FR60 Hardware Manual

CHAPTER 7 16-BIT FREE-RUNNING TIMER AND 16-BIT RELOAD TIMER
7.2.3

Operation of the 16-bit Reload Register

This section describes operation of the 16-bit reload register.
■ Clock Operation
If the timer operates with a divide-by clock of the clock, one of the clocks generated by dividing the
machine clock by 2, 8, or 32 can be selected as the count source. (In addition, in the case of ch3 only, up to
divide-by 64 or 128 clock can be selected.)
To start the count operation as soon as counting is enabled, write "1" to the CNTE and TRG bits of the
control status register.
Trigger input occurring due to the TRG bit is always valid regardless of the operating mode while the timer
is running (CNTE=1).
Figure 7.2-2 shows the startup and operations of the counter.
After the counter start trigger is inputted, Time T (T: peripheral clock machine cycle) is required until the
data of the reload register is loaded into the counter.
Count clock
Counter
Data load
CNTE (register)
TRG (register)
292
Figure 7.2-2 Startup and Operations of the Counter
Reload data
T
-1 -1 -1