Flag Register (Flg); Bit 0: Carry Flag (C Flag); Bit 1: Debug Flag (D Flag); Bit 2: Zero Flag (Z Flag) - Renesas R8C/Tiny Series Software Manual

Chapter 1 Overview

1.4 Flag Register (FLG)

Figure 1.4.1 shows the configuration of the flag register (FLG). The function of each flag is described
below.

1.4.1 Bit 0: Carry Flag (C Flag)

This flag holds bits carried, borrowed, or shifted-out by the arithmetic/logic unit.

1.4.2 Bit 1: Debug Flag (D Flag)

This flag enables a single-step interrupt.
When this flag is set to 1, a single-step interrupt is generated after an instruction is executed. When the
interrupt is acknowledged, the flag is cleared to 0.

1.4.3 Bit 2: Zero Flag (Z Flag)

This flag is set to 1 when an arithmetic operation results in 0; otherwise, its value is 0.

1.4.4 Bit 3: Sign Flag (S Flag)

This flag is set to 1 when an arithmetic operation results in a negative value; otherwise, its value is 0.

1.4.5 Bit 4: Register Bank Select Flag (B Flag)

This flag selects a register bank. If it is set to 0, register bank 0 is selected; if it is set to 1, register bank
1 is selected.

1.4.6 Bit 5: Overflow Flag (O Flag)

This flag is set to 1 when an arithmetic operation results in an overflow.
1.4.7 Bit 6: Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
When this flag is set to 0, the interrupt is disabled; when it is set to 1, the interrupt is enabled. When the
interrupt is acknowledged, the flag is cleared to 0.

1.4.8 Bit 7: Stack Pointer Select Flag (U Flag)

When this flag is set to 0, the interrupt stack pointer (ISP) is selected; when it is set to 1, the user stack
pointer (USP) is selected.
This flag is cleared to 0 when a hardware interrupt is acknowledged or an INT instruction is executed for
software interrupt numbers 0 to 31.

1.4.9 Bits 8 to 11: Reserved

Rev.2.00 Oct 17, 2005
REJ09B0001-0200
page 6 of 263
1.4 Flag Register (FLG)