Sdram Timing Register (Sdtr) - Motorola DigitalDNA ColdFire MCF5272 User Manual

9.5.2 SDRAM Timing Register (SDTR)

The SDTR is used to configure SDRAM controller refresh counters for the type of SDRAM
devices used and the number of clocks required for each type of SDRAM access. The reset
value is 0x2115. For lower CPU clock frequencies, precharge and activate times can be
reduced to eliminate up to 2 clock cycles from the read and write accesses. Consult the data
sheets of the SDRAMs being considered.
15
Write
Reset 0010_00
R/W
Addr
Table 9-8 describes SDTR fields.
Bits Name
15–10 RTP Refresh timer prescaler. Determines the number of clock cycles x 16 between refreshes. The
following table describes different recommended prescaler settings for different clock frequencies
including a margin of 1.2 µS. Recommended values are as follows:
9–8 RC Refresh count. Indicates the number of clock cycles spent in refresh state (RC + 5). Refresh occurs
during the first of these clock cycles; the rest of the time is the delay that must occur before the
SDRAM is ready to do anything else.
00 5 cycles
01 6 cycles (default)
10 7 cycles
11 8 cycles
7–6 — Reserved, should be cleared.
5–4 RP Precharge time. Specifies number of clock cycles taken for a precharge (RP + 1).
00 1 cycle
01 2 cycles (default)
10 3 cycles
11 4 cycles
10 9
RTP
Figure 9-4. SDRAM Timing Register (SDTR)
Table 9-8. SDTR Field Descriptions
RTP 15.6 µs = 1/f*RTP*16
111101
101011
011101
010110
000100
Chapter 9. SDRAM Controller
8 7 6 5
RC —
01 00
R/W
MBAR + 0x0184
Description
System Clock
61
43
29
22
4 5 MHz (emulator)
SDRAM Registers
4 3 2 1
RP RCD CLT
01 01
66 MHz
48 MHz
33 MHz
25 MHz
0
01
9-9