Table A-17 Rts Timing Summary; Table A-18 Tstw Timing Summary; Table A-19 Addressing Mode Timing Summary - Motorola DSP56800 Manual

The term "2 * ap" represents the two instruction fetches done by the
RTI/RTS instruction to refill the pipeline. The ax term represents fetching
the return address from the software stack when the stack pointer points to
external X memory, and the 2 * ax term includes both this fetch and the
fetch of the SR as performed by the RTI and RTS instructions.
Address Register Indirect
No update
Post-increment by 1
Post-decrement by 1
Post addition by offset Nn
Indexed by offset Nn
Special
Immediate data
Immediate short data
Absolute address
Absolute short address
I/O short address
Implicit
Indexed by short displacement
Indexed by long displacement
Table A-17. RTS Timing Summary
Operation
RTI, RTS
Table A-18. TSTW Timing Summary
TSTW Operation
Register
X memory
Table A-19. Addressing Mode Timing Summary
Effective Addressing Mode
Instruction Set Details
+rx Cycles
2 * ap + 2 * ax
NOTE:
+ tst Cycles
0
ea + ax
+ ea Words
0
0
0
0
0
1
0
1
0
0
0
0
1
+ ea Cycles
0
0
0
0
2
2
0
2
0
0
0
2
4
A-21