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CLKOUT
FC0–FC2
A15/DRAMA 14–
A1/DRAMA 0
AS
UDS, LDS
R/W
UW, LW
OE
DTACK
D15–D0
DRAMW
RAS
CAS
* NOTE: TAS IS A BYTE-ONLY INSTRUCTION, THEREFORE ONLY ONE OF UW, LW AND ONLY ONE CAS WILL BE ASSERTED.
Figure 8-11. DRAM Timing – 1-Wait, Test and Set
8.11 SERIAL MODULE ELECTRICAL CHARACTERISTICS
(T A = 0 C to 70 C, V CC = 5.0 V 5%, See Note 1)
X1/CLK Input Leakage Current
X1/CLK Frequency (see Note 2)
Counter/Timer Clock Frequency (IP2)
NOTES:
1. All voltage measurements are referenced to ground (GND). For testing, all input signals except X1/CLK swing
between 0.4 V and 2.4 V with a maximum transition time of 20 ns. For X1/CLK, this swing is between 0.4 V and
4.4 V. All time measurements are referenced at input and output voltages of 0.8 V and 2.0 V as appropriate.
Test conditions for outputs: C L = 150 pF, R L = 750
2. To use the standard baud rates selected by the clock-select register given in Tables 6-5 and 6-6, the X1/CLK
frequency should be set to 3.6864 MHz or a 3.6864 MHz crystal should be connected across pins X1/CLK and X2.
3. IP5–2 for RxC, TxC are not supported in the MC68306.
MOTOROLA
80
90
Characteristic
MC68306 USER'S MANUAL
79
91
Symbol
to V CC .
92
Min
Max
I X1L
2.5
f CLK
2.0
4.0
f CTC
0
16.67
Unit
A
MHz
MHz
8- 15
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