Command Set - Motorola MC68302 User Manual

The SCC to external memory path bypasses the dual-port RAM by allowing
the SDMA channel to arbitrate for the M68000 bus directly. The SCC to dual-
port RAM path saves external memory and eliminates the need to arbitrate
for the bus.
The SDMA channels are transparent to the user, implementing bus-cycle-
stealing data transfers controlled by microcode in the CP main controller.
Having no user-accessible registers associated with them, the channels are
effectively controlled by the choice of SCC configuration options. More in-
formation on the SDMA channels is contained in 3.1 OMA CONTROL.
4.3 COMMAND SET
The M68000 core processor (or an external processor) issues commands to
the CP by writing to the CP command register. The M68000 core should set
the least significant bit (FLG) of the command register when it issues com-
mands. The CP clears FLG after completing the command to indicate to the
M68000 core that it is ready for the next command. Subsequent commands
to the CP command register may be given only after FLG is cleared. The
software reset (issued with the RST bit) command may be given regardless
of the state of FLG, but the M68000 core should still set FLG when setting
RST.
The command register, an 8-bit, memory-mapped, read-write register, is
cleared by reset.
AST
I
GCI OPCODE
I --
CH. NUM. FLG
RST - Software Reset Command
This bit is set by the M68000 core and cleared by the CP. This command
is useful when the M68000 core wants to reset the registers and parameters
for all channels (SCCs, SCP, SMCs). The main controller in the CP detects
this command by hardware and resets the entire CP. Setting RST leaves
the CP in the same state as a hardware reset.
GCI - CGI Commands
MOTOROLA
1 =When set in conjunction with the opcode bits, this bit allows the two
GCI commands (ABORT REQUEST and TIMEOUT) to be generated.
The accompanying CH. NUMBER should be 10, and FLG should be
set.
MC68302 USER'S MANUAL 4-3