On-Chip Debug Support Concept - Infineon Technologies XC800 User Manual

2.2

On-Chip Debug Support Concept

The XC800 microcontrollers have an On-Chip Debug Support (OCDS) unit that provides
basic functionality to support software development and debugging of the XC800-based
systems. The debug functionality is usually enabled after the device has been started in
OCDS mode.
The debug concept is based on the interaction between the OCDS hardware and a
dedicated software (Monitor program) which is usually located in the Boot ROM.
Standard interface such as the JTAG or UART is used to communicate with an external
host (a debugger).
An overview of the debug interfaces is shown in
Primary
Debug
JTAG
Interface
Monitor &
Bootstrap loader
Control line
OCDS
Interrupt
NMI Report
System
Control
EVR Reset
Unit
CPU Reset
Clock
Alternate
Debug
UART
Interface
- parts of OCDS
Figure 2-3 XC800 OCDS Block Diagram
• A Monitor Mode Control (MMC) block at the center of the OCDS system brings
together control signals and supports the overall functionality
• MMC communicates with the XC800 core primarily via the Debug Interface, and also
receives reset and clock signals
• After processing memory address and control signals from the core, MMC provides
proper access to the dedicated memories: a Monitor ROM (holding the code) and a
Monitor RAM (for work-data and Monitor-stack)
User's Manual, V 0.1
JTAG M odule
TMS
TCK
TCK
TDI
TDI
TDO
TDO
Control
Reset
TxD
RxD
UART
2-18
Figure 2-3.
Flash
(Program M em ory)
Control
Memory
Configuration
Monitor Mode Control
Reset Clock Debug PROG PROG
Interface & IRAM Data
Addresses
XC800
XC800
CPU Architecture
M emory
Control
Unit
User Boot/
Program Monitor
Memory ROM
User M onitor
Internal RAM
RAM
Memory
Control
2005-01