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The CR Þelds can be set in one of the following ways:
¥ SpeciÞed Þelds of the CR can be set from a GPR by using the mtcrf instruction.
¥ An mcrf instruction can move the contents of XER[0Ð3] to a CR Þeld.
¥ An mcrxr instruction can copy a speciÞed XER Þeld to a speciÞed CR Þeld.
¥ Condition register logical instructions perform logical operations on speciÞed CR
bits.
¥ CR0 can be the implicit result of an integer instruction.
¥ A speciÞed CR Þeld can indicate the result of an integer compare instruction.
Note that branch instructions are provided to test individual CR bits.
5.1.1.1.2 Condition Register CR0 Field DeÞnition
For all integer instructions, when the CR is set to reßect the result of the operation (that is,
when Rc = 1), and for addic., andi., and andis., CR0[0Ð2] are set by an algebraic
comparison of the result to zero; CR0[3] is copied from XER[SO]. For integer instructions,
CR[0Ð3] reßects the result as a signed quantity.
The CR bits are interpreted as shown in Table 5-3. If any portion of the result is undeÞned,
the value placed into CR0[0Ð3] is undeÞned.
CR0 Bit
0
Negative (LT). Set when the result is negative.
1
Positive (GT). Set when the result is positive (and not zero).
2
Zero (EQ). Set when the result is zero.
3
Summary overßow (SO). This is a copy of the Þnal state of XER[SO] at the completion of the instruction.
Note that CR0 may not reßect the true (that is, inÞnitely precise) result if overßow occurs.
5.1.1.1.3 XER
Figure 5-2 shows XER bit assignments. Settings are based on the Þnal result produced by
executing an instruction.
Bit
0
1
2
Field
SO
OV
CA
Reset
R/W
Bit
16
17
18
Field
Reset
R/W
MOTOROLA
Table 5-3. Bit Settings for CR0 Field of CR
3
4
5
6
0000_0000_0000_0000
19
20
21
22
Ñ
0000_0000_0000_0000
Figure 5-2. XER Register
Chapter 5. PowerPC Core Register Set
Part II. PowerPC Microprocessor Module
Description
7
8
9
10
Ñ
R/W
23
24
25
26
R/W
11
12
13
14
27
28
29
30
BCNT
15
31
5-3
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