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Table 3-3. Development Support SPRs
SPR Number
(Decimal)
1
All development-support SPRs are implementation-specific.
Unless otherwise noted, reserved fields in registers are ignored when written and return
zero when read. An exception to this rule is XER[16:23] (See <st-bold>3.7.5.). These bits
are set to the value written to them and return that value when read.
3.7
User Instruction Set Architecture (UISA)
Register Set
The UISA registers can be accessed by either user- or supervisor-level instructions. The
general-purpose registers are accessed through instruction operands.
3.7.1
General-Purpose Registers (GPRs)
Integer data is manipulated in the integer unit's thirty-two 32-bit GPRs, shown below.
These registers are accessed as source and destination registers through operands in the
instruction syntax.
MSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 LSB
0
Reset
Figure 3-4. General-Purpose Registers (GPRs)
3.7.2
Floating-Point Registers (FPRs)
The MPC500 architecture provides 32 64-bit FPRs. These registers are accessed as source
and destination registers through operands in floating-point instructions. Each FPR
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Special-Purpose Register
158
I-bus Support Control Register (ICTRL)
See Table 21-28 for bit descriptions.
159
Breakpoint Address Register (BAR)
See Table 21-22 for bit descriptions.
630
Development Port Data Register (DPDR)
See Section 21.6.13, "Development Port Data Register
(DPDR)," for bit descriptions.
Chapter 3. Central Processing Unit
User Instruction Set Architecture (UISA) Register Set
1
(continued)
GPR0
GPR1
. . .
. . .
GPR31
Unchanged
31
3-13
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