Pit As A "Free-Running" Timer; Interval Timer Registers; Counter Reloading From The Modulus Latch; Counter In Free-Running Mode - Motorola M-CORE MMC2001 Series Reference Manual

When the counter reaches a count of zero, the PIT interrupt flag (ITIF) is set in the
ITCSR and the value in the modulus latch is loaded into the counter to be decre-
mented towards zero. If the PIT interrupt enable (ITIE) bit is set in the ITCSR, the
interrupt flag issues an interrupt to the CPU.
The counter may by directly initialized, without having to wait for the count to reach
zero, when the ITDR is written with the OVW bit in the ITCSR set.
OSC
OSC/4
0x0002
COUNTER
MODULUS
ITIF
Figure 9-14 Counter Reloading from the Modulus Latch

9.6.3 PIT as a "Free-Running" Timer

This mode of operation is selected when the RLD bit in the ITCSR is cleared to a
value of zero. In this mode, the counter rolls over from 0x0000 to 0xFFFF, without
reloading from the modulus latch, and continues to count.
When the counter reaches a count of zero, the PIT interrupt flag (ITIF) is set in the
ITCSR. If the PIT interrupt enable (ITIE) bit is set in the ITCSR, the interrupt flag can
issue an interrupt to the CPU.
The counter may by directly initialized, without having to wait for the count to reach
zero, when the ITDR is written while the OVW bit is set.
OSC
OSC/4
COUNTER 0x0002
MODULUS
ITIF

9.6.4 Interval Timer Registers

The interval timer has three registers: the control/status register (ITCSR), the data
register (ITDR), and the alternate data register (ITADR).
MMC2001
REFERENCE MANUAL
Freescale Semiconductor, Inc.
0x0001
0x0001
Figure 9-15 Counter in Free-Running Mode
TIMER/RESET MODULE
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0x0000
0x0005
0x0000
0x0005
0x0005
0xFFFF
MOTOROLA
9-13