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WSTP — Watchdog Stop Enable (one-time writable)
0 = Watchdog not affected in stop mode
1 = Watchdog disabled in stop mode
WDE — Watchdog Enable (one-time writable)
0 = Watchdog is disabled
1 = Watchdog is enabled (once set, watchdog cannot be disabled)
WDBG — Watchdog Debug Enable (one-time writable)
0 = Watchdog not affected in debug mode
1 = Watchdog disabled in debug mode
WDZE — Watchdog Doze Enable (one-time writable)
0 = Watchdog not affected in doze mode
1 = Watchdog disabled in doze mode
9.5.8.2 Watchdog Service Register (WSR)
When enabled, the watchdog requires that a service sequence be written to the
watchdog service register (WSR). This register controls the clearing of the watchdog
counter to keep it from timing out and causing a reset. If this register is not written
with 0x5555 followed by 0xAAAA before the selected rate expires, the watchdog sets
the WDR bit in the reset source register and asserts a system reset.
Both writes must occur in the order listed prior to the time-out, but any number of
instructions can be executed between the two writes.
Access this register with 32-bit loads and stores only.
WSR — Watchdog Service Register
31
30
29
28
R
0
0
0
0
W
RESET:
15
14
13
12
R
0
0
0
0
W
RESET:
0
0
0
0
9.6 Interval Timer (PIT)
The interval timer (PIT) is a 16-bit "set-and-forget" timer that provides precise inter-
rupts at regular intervals with minimal processor intervention. The timer can either
count down from the value written in the modulus latch, or it can be a free-running
down-counter.
MMC2001
REFERENCE MANUAL
All manuals and user guides at all-guides.com
Freescale Semiconductor, Inc.
27
26
25
24
0
0
0
0
11
10
9
8
0
0
0
0
WATCHDOG SERVICE REGISTER
0
0
0
0
Figure 9-11 Watchdog Service Register
TIMER/RESET MODULE
For More Information On This Product,
Go to: www.freescale.com
23
22
21
20
0
0
0
0
7
6
5
4
0
0
0
0
0
0
0
0
10001020
19
18
17
16
0
0
0
0
3
2
1
0
0
0
0
0
0
0
0
0
MOTOROLA
9-11
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