Cop Watchdog Reset; Cop Reset And Rti Rates - Motorola MC68HC05T16 Technical Data Manual

IRQN - IRQ Pin Trigger Option
1 (set) – Negative edge triggering for IRQ only.
0 (clear) – Level and negative edge triggering for IRQ.
WDOG - COP Watchdog Enable
1 (set) – COP watchdog circuit enabled.
0 (clear) – COP watchdog circuit disabled.
See Section 5.2.1 on COP watchdog reset.
RT1, RT0 - Rate Select for COP watchdog and RTI
See Section 5.2.1 on watchdog reset.
5.2.1

COP Watchdog Reset

The COP (Computer Operating Properly) watchdog timer function is implemented by using the
output of the Multi-Function Timer counter. The minimum COP reset rates are controlled by RT0
and RT1 of Multi-Function Timer register. If the COP circuit times out, an internal reset is
generated and the reset vector is fetched (at $FFFE & $FFFF). Preventing a COP time-out is
achieved by writing a '0' to bit 0 of address $FFF0. The COP counter has to be cleared periodically
by software with a period less than COP reset rate.
Watchdog timer function will stop counting in Wait and Stop modes. Counting continues when it
wakes up from Wait mode, and a 4064 cycle delay after waking up from Stop mode.
The watchdog counter system is controlled by the WDOG bit in the Multi-Function Timer register
(bit 2 of address $1C). After power-on or external reset the watchdog system is disabled. Writing
a "1" to the WDOG bit will enable the watchdog system and the counter starts counting. Once
enabled, the watchdog system cannot be disabled by software. Writing a "0" to bit 0 of address
$FFF0 will reset watchdog counter to prevent a watchdog time-out.
RT1
0
0
1
1
RT0 and RT1 should only be changed immediately after COP watchdog timer has been reset.
MC68HC05T16
Table 5-1 COP Reset and RTI Rates
Minimum COP reset period
RT0
E clock = 4.2MHz
0 27.3ms
1 54.6ms
0 109.27ms
1 218.4ms
TIMERS
RTI period
E clock = 4.2MHz
3.9ms
7.8ms
15.6ms
31.2ms
MOTOROLA
5
TPG
5-11