Table 79. TIPB Access Rates
Number of Wait States
0
1
2
3
4
5
6
7
SPRU890A
Total Strobe Period
(in DSP core clock cycles)
Each access factor field in the control mode register controls the access rate
for a group of peripherals. Table 80 and Table 81 show the peripherals that are
affected by the ACCESS_FACTOR0 and ACCESS_FACTOR1 bits for
OMAP5912 and OMAP5910, respectively.
2
3
4
5
6
7
8
9
TI Peripheral Bus Bridges
Equivalent Access Rate
DSP clock divided by 2
DSP clock divided by 3
DSP clock divided by 4
DSP clock divided by 5
DSP clock divided by 6
DSP clock divided by 7
DSP clock divided by 8
DSP clock divided by 9
DSP Subsystem
189