RM0401
12.5.3
DAC output voltage
Digital inputs are converted to output voltages on a linear conversion between 0 and V
The analog output voltages on each DAC channel pin are determined by the following
equation:
DACoutput
12.5.4
DAC trigger selection
If the TENx control bit is set, conversion can then be triggered by an external event (timer
counter, external interrupt line). The TSELx[2:0] control bits determine which possible
events will trigger conversion as shown in
TIM5 TRGO event
EXTI line9
SWTRIG
Each time a DAC interface detects a rising edge on the selected timer TRGO output, or on
the selected external interrupt line 9, the last data stored into the DAC_DHRx register are
transferred into the DAC_DORx register. The DAC_DORx register is updated three APB1
cycles after the trigger occurs.
If the software trigger is selected, the conversion starts once the SWTRIG bit is set.
SWTRIG is reset by hardware once the DAC_DORx register has been loaded with the
DAC_DHRx register contents.
Note:
TSELx[2:0] bit cannot be changed when the ENx bit is set. When software trigger is
selected, the transfer from the DAC_DHRx register to the DAC_DORx register takes only
one APB1 clock cycle.
DOR
V
×
=
------------- -
REF+
4096
Table 52. External triggers
Source
Internal signal from on-chip
timers
External pin
Software control bit
RM0401 Rev 3
Digital-to-analog converter (DAC)
Table
52.
Type
.
REF+
TSEL[2:0]
011
110
111
247/771
256
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