Gpiox Output Data Register (Gpiox_Odr) (X = A To B); Gpiox Bit Set/Reset Register (Gpiox_Bsrr) (X = A To B) - ST STM32WL5 Series Reference Manual

Advanced arm-based 32-bit mcus with sub-ghz radio solution

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Table of Contents

General-purpose I/Os (GPIO)

GPIOx output data register (GPIOx_ODR) (x = A to B)

Address offset: Block A: 0x0014

Address offset: Block B: 0x0414

Reset value: 0x0000 0000

Bits 31:16 Reserved, must be kept at reset value.

Bits 15:0 OD[15:0]: Port Px[15:0] output data

These bits can be read and written by software.

Note: For atomic bit set/reset, OD bits can be individually set and/or reset by writing to the

Address offset: Block A: 0x0018

Address offset: Block B: 0x0418

Reset value: 0x0000 0000

Bits 31:16 BR[15:0]: Port Px[15:0] reset output data bit [15:0] in GPIOx_ODR

Note: If both BSy and BRy are set, BSy has priority.

Bits 15:0 BS[15:0]: Port Px[15:0] set output data bit [15:0] in GPIOx_ODR

GPIOx_BSRR and GPIOx_BRR registers.

These bits are read clear-write 1. A read to these bits returns the value 0x0000.

0: No action on the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15)

1: Resets the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15).

These bits are read clear-write 1. A read to these bits returns the value 0x0000.

0: No action on the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15)

1: Sets the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15).

RM0453 Rev 1

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