Gpiox Bit Reset Register (Gpiox_Brr) (X = A To B); Gpioc Mode Register (Gpioc_Moder) - ST STM32WL5 Series Reference Manual

RM0453
Bits 19:16 AFSEL12[3:0]: Port Px12 alternate function selection
Bits 15:12 AFSEL11[3:0]: Port Px11 alternate function selection
Bits 11:8 AFSEL10[3:0]: Port Px10 alternate function selection
Bits 7:4 AFSEL9[3:0]: Port Px9 alternate function selection
Bits 3:0 AFSEL8[3:0]: Port Px8 alternate function selection
These bits are written by software to configure alternate function I/Os
0x0: AF0 selected
0x1: AF1 selected
0x2: AF2 selected
...
0xE: AF14 selected
0xF: AF15 selected
10.4.11

GPIOx bit reset register (GPIOx_BRR) (x = A to B)

Address offset: Block A: 0x0028
Address offset: Block B: 0x0428
Reset value: 0x0000 0000
31 30 29
Res. Res. Res.
15 14 13
BR15 BR14 BR13 BR12
rc_w1 rc_w1 rc_w1 rc_w1
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:0 BR[15:0]: Port Px[15:0] reset output data bit [15:0] in GPIOx_ODR.
10.4.12

GPIOC mode register (GPIOC_MODER)

Address offset: 0x0800
Reset value: 0xFC00 3FFF
31 30 29 28
MODE15[1:0] MODE14[1:0]
rw rw rw rw
15 14 13 12
Res. Res. MODE6[1:0]
rw rw
28 27 26 25
Res. Res. Res. Res.
12 11 10 9
BR11 BR10 BR9
rc_w1 rc_w1 rc_w1
These bits are read clear-write 1. A read to these bits returns the value 0x0000.
0: No action on the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15)
1: Resets the corresponding GPIOx_ODR.OD[y] bit (y = 0 to 15).
27 26 25
MODE13[1:0] Res.
rw rw
11 10 9
MODE5[1:0] MODE4[1:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
BR8 BR7 BR6
rc_w1 rc_w1 rc_w1
24 23 22
Res. Res. Res. Res.
8 7 6
MODE3[1:0]
rw rw rw
RM0453 Rev 1
General-purpose I/Os (GPIO)
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
BR5 BR4 BR3 BR2
rc_w1 rc_w1 rc_w1 rc_w1
21 20 19 18
Res. Res. Res.
5 4 3 2
MODE2[1:0] MODE1[1:0]
rw rw rw rw
17 16
Res. Res.
1 0
BR1 BR0
rc_w1 rc_w1
17 16
Res. Res.
1 0
MODE0[1:0]
rw rw
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