Gpioc Pull-Up/Pull-Down Register (Gpioc_Pupdr); Gpioc Input Data Register (Gpioc_Idr) - ST STM32WL5 Series Reference Manual

General-purpose I/Os (GPIO)
10.4.15

GPIOC pull-up/pull-down register (GPIOC_PUPDR)

Address offset: 0x080C
Reset value: 0x0000 0000
31 30 29 28
PUPD15[1:0] PUPD14[1:0]
rw rw rw rw
15 14 13 12
Res. Res. PUPD6[1:0]
rw rw
Bits 31:30 PUPD15[1:0]: Port PC15 pull configuration
Bits 29:28 PUPD14[1:0]: Port PC14 pull configuration
Bits 27:26 PUPD13[1:0]: Port PC13 pull configuration
Bits 25:14 Reserved, must be kept at reset value.
Bits 13:12 PUPD6[1:0]: Port PC6 pull configuration
Bits 11:10 PUPD5[1:0]: Port PC5 pull configuration
Bits 9:8 PUPD4[1:0]: Port PC4 pull configuration
Bits 7:6 PUPD3[1:0]: Port PC3 pull configuration
Bits 5:4 PUPD2[1:0]: Port PC2 pull configuration
Bits 3:2 PUPD1[1:0]: Port PC1 pull configuration
Bits 1:0 PUPD0[1:0]: Port PC0 pull configuration
10.4.16

GPIOC input data register (GPIOC_IDR)

Address offset: 0x0810
Reset value: 0x0000 XXXX
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
ID15 ID14 ID13 Res.
r r r
Bits 31:16 Reserved, must be kept at reset value.
Bit 15 ID15: Port PC15 input data bit
Bit 14 ID14: Port PC14 input data bit
412/1461
27 26 25
PUPD13[1:0] Res.
rw rw
11 10 9
PUPD5[1:0] PUPD4[1:0]
rw rw rw
These bits are written by software to configure the I/O pull-up or pull-down.
00: No pull-up, pull-down
01: Pull-up
10: Pull-down
11: Reserved
27 26 25
Res. Res. Res.
11 10 9
Res. Res. Res.
24 23 22
Res. Res. Res. Res.
8 7 6
PUPD3[1:0]
rw rw rw
24 23 22
Res. Res. Res. Res.
8 7 6
Res. Res. ID6 ID5
r
RM0453 Rev 1
21 20 19 18
Res. Res. Res.
5 4 3 2
PUPD2[1:0] PUPD1[1:0]
rw rw rw rw
21 20 19 18
Res. Res. Res.
5 4 3 2
ID4 ID3 ID2
r r r r
RM0453
17 16
Res. Res.
1 0
PUPD0[1:0]
rw rw
17 16
Res. Res.
1 0
ID1 ID0
r r