Ppg0 Operation Mode Control Register (Ppgc0) - Fujitsu F2MC-16LX MB90580 Series Hardware Manual

14.3.1 PPG0 operation mode control register (PPGC0)

PPG0 operation mode control register
Address: ch0 000044H
PPGC0 is a five-bit control register that selects the operation mode of the block, controls pin outputs,
selects count clock, and controls triggers.
[bit 7] PEN0 (PPG enable): Operation enable bit
This bit selects the PPG operation mode as described below.
PEN0
0
1
Setting this bit to 1 makes the PPG start counting.
This bit is initialized to '0' upon a reset. This bit is readable and writable.
[bit 5] PE00 (PPG output enable 0): PPG0 pin output enable bit
This bit controls the PPG0 pulse output external pin as described below.
PE00
0
1
This bit is initialized to '0' upon a reset. This bit is readable and writable.
[bit 4] PIE0 (PPG interrupt enable): PPG interrupt enable bit
This bit controls PPG interrupt as described below.
PIE0
0
1
While '1' is written to this bit, an interrupt request is issued as soon as '1' is written to PUF0. No inter-
rupt request is issued while this bit is set to '0.'
This bit is initialized to '0' upon a reset. This bit is readable and writable.
Note: PIE0 is assigned the same interrupt vector number as that of 16-bit reload timer.
When using EI
[bit 3] PUF0 (PPG underflow flag): PPG counter underflow bit
MB90580 Series
7
PEN0
Read/write (R/W)
(0)
Initial value
Operation
Stop ('L' level output maintained)
PPG operation enabled
General-purpose port pin (pulse output disabled)
PPG0 = pulse output pin (pulse output enabled)
Operation
Interrupt disabled
Interrupt enabled
2
OS in 16-bit reload timer, write '0' to PIE0.
6 5 4 3
PE00 PIE0 PUF0
(-) (R/W) (R/W) (R/W)
(X) (0) (0) (0)
[initial value]
Operation
[initial value]
14.3 Registers and Register Details
Bit No.
2 1 0
Reserved
PPGC0
(-) (-) (-)
(X) (X) (1)
[initial value]
Chapter 14: 8/16-Bit PPG 195