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10.2 Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) is used for the start and clearing of the
watchdog timer and the display of reset causes.
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Watchdog timer control register (WDTC)
Figure 10.2-1 shows the configuration of the watchdog timer control register (WDTC), and Table
10.2-1 explains the function of each bit in the WDTC register.
Address
bit15
0000A8
H
R
: Read only
W
: Write only
x
: Undefined
-
: Undefined
*
: The previous state is held.
: Default value
The interval time is 3.5 to 4.5 times as large as the count clock (output value of the timebase
timer) cycle. See Section "10.4 Watchdog Timer Operation", for details.
Figure 10.2-1 Watchdog timer control register (WDTC)
bit8
bit7
bit6
(TBTC)
PONR
Reserved
R
Interval time selection bit (at HCLK: 4 MHz; SCLK: 32 kHz)
WT1 WT0
WDCS
& SCM
0
0
1
Approximately 3.58 ms
0
1
1
Approximately 14.33 ms Approximately 18.3 ms
1
0
1
Approximately 57.23 ms Approximately 73.73 ms
0
1
1
Approximately 458.75 ms Approximately 589.82 ms
0
0
0
Approximately 0.457 s
0
1
0
Approximately 3.584 s
1
0
0
Approximately 7.168 s
1
1
0
Approximately 14.336 s
HCLK: Oscillation clock
SCLK: Sub-clock
WTE
Starts the watchdog timer
(at first write event after reset)
0
Clears the watchdog timer
(at second write event after reset)
No operation
1
Undefined bit
Reset cause bits
PONR WRST ERST SRST
1
X
*
1
*
*
*
*
CHAPTER 10 WATCHDOG TIMER
bit5
bit4
bit3
bit2
bit1
WRST
ERST SRST WTE WT1 WT0
R
R
R
W
W
Interval time
Minimum
Maximum
Approximately 4.61 ms
Approximately 0.576 s
Approximately 4.608 s
Approximately 9.216 s
Approximately 18.432 s
Watchdog control bit
Reading and writing has no effect on operation
Reset cause
X
X
Power on
*
*
Watchdog timer
1
*
External pin (RST = "L" input)
*
1
RST bit (software reset)
bit0
Initial value
XXXXX111
B
W
Number of oscillation
clock cycles
14
± 2
11
(2
)/HCLK cycles
± 2
16
13
(2
)/HCLK cycles
18
± 2
15
(2
)/HCLK cycles
21
± 2
18
(2
)/HCLK cycles
12
± 2
9
(2
)/SCLK cycles
15
± 2
12
(2
)/SCLK cycles
16
± 2
13
(2
)/SCLK cycles
17
± 2
14
(2
)/SCLK cycles
201
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