Watchdog Timer Control Register (Wdtc) - Fujitsu F2MC-16LX Hardware Manual

9.2

Watchdog Timer Control Register (WDTC)

The watchdog timer control register (WDTC) activates and clears the watchdog timer
and displays a reset cause.
■ Watchdog Timer Control Register (WDTC)
Watchdog control register
Address:0000A8
Read/write
Initial value
Note:
Because access by read modify instructions causes malfunctions, do not use the read
modify instructions to obtain access.
[bit7 to bit3] PONR, STBR, WRST, ERST, and SRST
These bits are flags for indicating reset sources and are set by each reset as shown in Table
9.2-1. After the WDTC register read operation, all bits are cleared to "0".
This is a read only register.
Table 9.2-1 PONR, STBR, WRST, ERST, and SRST (for Sources of Resets)
Power-on
Hardware standby
Watchdog timer
External pin
RST bit
*: Retains the previous value.
[bit2] WTE
When the watchdog timer stops and "0" is written in WTE, the watchdog timer becomes
operable. Second and subsequent "0" writings clear the watchdog timer counter. Writing "1"
does not result in an operation.
The watchdog timer stops by power-on, hardware standby, or reset by the watchdog timer.
Value "1" is read at reading.
[bit1, bit0] WT1 and WT0
WT1 and WT0 bits are used to select an interval time of the watchdog timer. Only data
written during watchdog timer activation is valid.
watchdog timer activation is ignored. These bits are writable only.
Figure 9.2-1 Watchdog Timer Control Register (WDTC)
7 6
bit
PONR STBR WRST ERST SRST
H
(R) (R)
(X) (X)
Reset cause
9.2 Watchdog Timer Control Register (WDTC)
5 4 2
3
WTE
(R) (R) (R) (W)
(X) (X) (X) (1)
PONR STBR
1 -
1
*
* *
* *
* *
Data written at operation other than
1 0
WT1 WT0 WDTC
(W) (W)
(1) (1)
WRST ERST
- -
* *
1
*
1
*
* *
SRST
-
*
*
*
1
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