Program Address Detection Control Status Register (Pacsr) - Fujitsu MB90480 Series Hardware Manual

21.3.1 Program Address Detection Control Status Register
(PACSR)
The program address detection control status register (PACSR) enables or disables
output of an interrupt at an address match. If an address match is detected when
output of an interrupt at an address match is enabled, the INT9 interrupt is output.
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Program Address Detection Control Status Register (PACSR)

Figure 21.3-2 Program Address Detection Control Status Register (PACSR)
7
R/W R/W
R/W : Readable/Writable
6
5 4 3 2 1
R/W R/W R/W R/W R/W
: Initial value
CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
0
Initial value
00000000
B
R/W
bit 0
Reserved
0 Always set to "0"
bit 1
Address match detection enable bit 0
ADE0
0
Disables address match detection in PADR0
1
Enables address match detection in PADR0
bit 2
Reserved
0 Always set to "0"
bit 3
Address match detection enable bit 1
ADE1
0 Disables address match detection in PADR1
1
Enables address match detection in PADR1
bit 4
Reserved
Always set to "0"
0
bit 5
Reserved
0 Always set to "0"
bit 6
Reserved
0 Always set to "0"
bit 7
Reserved
0 Always set to "0"
Address
009E
H
Reserved bit
Reserved bit
Reserved bit
Reserved bit
Reserved bit
Reserved bit
461